1. Field of the Invention:
The present invention relates to a serial access memory device, and more particularly to a cascade buffer circuit for a serial access memory system whose word length or bit width can be extend by connecting memories in cascade.
2. Description of the Related Art:
Serial access memory systems such as First-In First-Out (FIFO) memory systems have been utilized in the field of signal processing particularly for signal processing. The serial access memory system is usually comprised of a serial memory section having a plurality of serial access storage locations and a cascade buffer circuit for controlling the operations of the serial memory section and indicating the state of the serial memory section to outside the memory. When a plurality of memories are connected in cascade to extend total word length or bit width, the cascade buffer circuit of the memory of one stage receives a read input control signal or a write input control signal from the previous, lower stage in order to perform a read operation on a operation of the memory of this one stage and produces a read output control signal or a write output control signal of the cascade buffer circuit of the memory in the subsequent stage, upper stage for designating a read or write operation to the memory of the upper stage. Thus, serial read or write operations can be conducted over the plurality of memories connected in cascade. Moreover, it is necessary to indicate a location in the cascade connection of the memories to at least the first or last memory to control start or end of the serial access operations, and a control terminal for inputting this kind of information to the memory, the cascade buffer circuit must be provided with the above control signal. Thus, the cascade buffer circuit of the memory system requires five terminals receiving the write input control signal, read input control signal, the write output control signal, the read output control signal and the signal indicating the location of the memory in the cascade connection.
Thus, the cascade buffer circuit of the memory system in the prior art necessitates five external terminals in a total. Since, the serial access memory section of the memory system needs relatively large number of terminals for fundamental memory action, the addition of the terminals for the cascade buffer circuit results in a considerably large number of terminals. This is large obstacle to reduce the size of the memory device and fabricate a large capacity of memory with a high density structure.